• Learning center

    Index/
    15. Intel 100 Series Chipset Architecture
    Today let's learn about the motherboard architecture of the Intel 100 series chipset.
    33 person
    Collection
    Detail
    Comments

    1

    00:00:00,166 --> 00:00:01,300

    Hello,everyone

    2

    00:00:01,433 --> 00:00:06,633

    Today let's learn about the motherboard architecture of the Intel 100 series chipset

    3

    00:00:07,500 --> 00:00:12,866

    The diagram we see now is the Intel 100 series chipset architecture diagram

    4

    00:00:13,066 --> 00:00:17,500

    This PCH is the PCH (Platform Controller Hub) of the Intel 100 series

    5

    00:00:18,000 --> 00:00:22,400

    It is paired with Intel's 6th and 7th generation CPUs

    6

    00:00:22,900 --> 00:00:25,966

    CPU manages memory through the memory bus

    7

    00:00:28,233 --> 00:00:33,133

    The CPU directly outputs the eDP (Embedded DisplayPort) display signal to the display screen

    8

    00:00:33,933 --> 00:00:37,633

    The graphics card function is integrated inside the CPU

    9

    00:00:37,833 --> 00:00:44,066

    At the same time, the CPU also manages the discrete graphics card through the PEG (PCI Express Graphics) bus

    10

    00:00:44,433 --> 00:00:51,233

    The display signal of the HDMI (High Definition Multimedia Interface) interface is output by the discrete graphics card

    11

    00:00:51,600 --> 00:00:56,366

    The communication between the PCH and the CPU is carried out through the DMI (Direct Media Interface) bus

    12

    00:00:56,833 --> 00:01:00,266

    PCH manages SATA devices such as hard drives

    13

    00:01:01,833 --> 00:01:03,100

    Through SATA (Serial Advanced Technology Attachment) bus

    14

    00:01:03,400 --> 00:01:14,100

    PCH also manages solid state drives, wireless network cards, Bluetooth and wired network cards, card readers, etc.

    15

    00:01:14,900 --> 00:01:17,933

    These devices pass through the PCIE (Peripheral Component Interface Extend) bus

    16

    00:01:18,233 --> 00:01:21,766

    EC (Embedded Controller) managed by PCH through LPC (Low pin count Bus) bus

    17

    00:01:22,133 --> 00:01:24,533

    EC manages touchpad and keyboard

    18

    00:01:25,333 --> 00:01:27,600

    PCH through SPI (SerialPerripheral Interface) bus

    19

    00:01:27,666 --> 00:01:29,533

    connects to the BIOS chip

    20

    00:01:29,700 --> 00:01:35,533

    PCH manages the sound card and communicates with the sound card through the sound card bus

    21

    00:01:35,966 --> 00:01:41,400

    The sound card manages the speakers and headphone jacks, as well as the microphone

    22

    00:01:42,633 --> 00:01:50,733

    The USB bus goes to the USB 3.0 interface, Type-C interface, camera, and fingerprint recognition

    23

    00:01:51,866 --> 00:01:56,000

    Well, this is the Intel 100 series chipset architecture diagram

    No comments yet
    Come and write your comments
    Related recommendations
    1/1
    Video
    115. BIOS structure introduction
    ¥0.00
    38 people are learning
    Series of lessons
    LCD backlight screen circuit maintenance
    ¥0.00
    33 people are learning
    Video
    167. Intel 6th~9th Power supplies generation seque
    ¥0.00
    40 people are learning
    Video
    354. I2S bus from baseband to CPU of iPhone 12 12 Pro
    ¥0.00
    37 people are learning
    Video
    192. Network card introduction
    ¥0.00
    82 people are learning
    Next lesson
    Video
    Xinzhizao Download and Install Redemption Code Instructions
    0 people are learning
    Links：