• Learning center

18.Intel 6~7 generation single CPU architecture
Let's learn about Intel's 6th and 7th generation low-power CPU architecture.
Detail
Comments

1

00:00:00,300 --> 00:00:07,066

Hello everyone, let's learn about Intel's 6th and 7th generation low-power CPU architecture

2

00:00:07,800 --> 00:00:15,400

This is an architecture diagram of a notebook motherboard using Intel's 6th and 7th generation low-power CPUs

3

00:00:18,266 --> 00:00:23,133

Intel's 6th and 7th generation low-power CPUs are like this

4

00:00:23,866 --> 00:00:26,833

It has CPU cores and PCH cores

5

00:00:27,166 --> 00:00:32,066

CPU still outputs the eDP display signal to the screen interface

6

00:00:32,366 --> 00:00:33,733

For screen display

7

00:00:34,066 --> 00:00:40,266

CPU sends a display signal through this DDI bus for the HDMI interface

8

00:00:41,366 --> 00:00:44,566

CPU internal integrates graphics card function

9

00:00:44,566 --> 00:00:50,200

At the same time, the discrete graphics card is managed through the PCIE bus

10

00:00:50,300 --> 00:00:54,466

The discrete graphics card is connected to DDR5 memory

11

00:00:54,866 --> 00:01:02,066

CPU is connected to the EC through the LPC bus and is responsible for communicating with the EC

12

00:01:02,533 --> 00:01:05,400

EC manages the touchpad and keyboard

13

00:01:05,600 --> 00:01:10,800

It also manages temperature control circuits, fans, etc.

14

00:01:11,266 --> 00:01:15,800

EC and CPU share one BIOS via SPI bus

15

00:01:16,566 --> 00:01:20,833

CPU manages the sound card chip through the sound card bus

16

00:01:21,300 --> 00:01:30,200

The sound card chip is connected with speakers, digital microphones, as well as headphone and microphone interfaces

17

00:01:30,566 --> 00:01:33,900

CPU manages WiFi through PCIE bus

18

00:01:34,433 --> 00:01:39,266

This bluetooth communicates via the USB 2.0 bus

19

00:01:39,633 --> 00:01:45,366

WiFi communicates with CPU through PCIE bus and is managed by PCH

20

00:01:46,366 --> 00:01:50,566

The SSD is managed by the CPU through the PCIE bus

21

00:01:52,333 --> 00:01:56,233

SATA hard disk is managed by CPU through SATA bus

22

00:01:56,833 --> 00:02:02,733

This red part and this green part usually refer to the part that is not used in the motherboard

23

00:02:03,000 --> 00:02:05,366

It is a function reserved by the motherboard

24

00:02:06,166 --> 00:02:11,466

USB 2.0 bus goes to USB interface, USB device

25

00:02:12,633 --> 00:02:20,366

Such as camera, fingerprint recognition and some Type-C interfaces, USB interfaces, etc.

26

00:02:20,866 --> 00:02:26,533

The USB interface has both USB 3.0 and USB 2.0 functions

27

00:02:27,466 --> 00:02:31,400

CPU manages the DDR4 memory through the memory bus

28

00:02:31,733 --> 00:02:36,733

Well, this is the Intel 6th and 7th generation low-power CPU architecture

No comments yet
Come and write your comments
Links: