• Learning center

19.Intel 500 Series Chipset Architecture
Let's learn about the Intel 500 series chipset motherboard architecture diagram.
Detail
Comments

1

00:00:00,400 --> 00:00:06,866

Hello everyone, let's learn about the Intel 500 series chipset motherboard architecture diagram

2

00:00:07,600 --> 00:00:11,900

This is a 500 series notebook motherboard architecture diagram

3

00:00:11,966 --> 00:00:19,333

This is PCH, the model is HM570, which belongs to the 500 series

4

00:00:19,766 --> 00:00:22,366

This is the 11th generation CPU

5

00:00:22,566 --> 00:00:26,633

CPU manages DDR4 memory through this memory bus

6

00:00:27,200 --> 00:00:29,066

There are 2 memory slots

7

00:00:29,200 --> 00:00:32,966

Discrete graphics card managed through PEG bus

8

00:00:33,566 --> 00:00:41,233

The display signal of HDMI interface and MINI DP interface are directly output by discrete graphics card

9

00:00:41,600 --> 00:00:46,900

This DDI is the display signal sent by the CPU to the eDP screen

10

00:00:47,566 --> 00:00:50,733

DDI is also called digital display port

11

00:00:51,033 --> 00:00:54,600

CPU manages two SSDs through the PCIE bus

12

00:00:55,000 --> 00:00:58,666

CPU communicates with PCH through DMI bus

13

00:00:59,100 --> 00:01:01,833

PCH reads BIOS through SPI bus

14

00:01:02,300 --> 00:01:08,066

This SPI ROM is the BIOS chip we often say, its capacity is 16MB

15

00:01:08,400 --> 00:01:16,700

PCH also manages Type-C interface, USB 3.0 interface, and SATA hard disk such as HDD

16

00:01:17,133 --> 00:01:19,300

It also manages the network card

17

00:01:19,700 --> 00:01:23,666

Here is the RJ45 interface of the network card chip

18

00:01:23,833 --> 00:01:30,700

Also manages WiFi, Bluetooth, as well as camera, fingerprint recognition and touch

19

00:01:31,733 --> 00:01:35,666

The sound card chip managed by the PCH through the sound card bus

20

00:01:35,800 --> 00:01:43,766

The sound card chip manages the headphone and microphone interfaces, as well as the digital microphone and speakers

21

00:01:44,433 --> 00:01:48,366

The PCH manages the touchpad through the I2C bus

22

00:01:48,700 --> 00:01:55,166

The touchpad also communicates with the EC, which is connected to the EC through the PS/2 bus

23

00:01:55,633 --> 00:02:01,000

PCH communicates with EC through LPC bus or eSPI bus

24

00:02:01,300 --> 00:02:05,500

The EC manages the keyboard, and the fans...etc

25

00:02:05,866 --> 00:02:16,633

Compared with our previous 300 series and 400 series architectures, the biggest feature of this architecture is that the SSD is managed by the CPU

26

00:02:17,433 --> 00:02:25,833

In the previous architecture of the 300 series and 400 series, the SSD was managed by the PCH through the PCIE bus

27

00:02:26,600 --> 00:02:30,833

Ok, here is the Intel 500 series architecture diagram

No comments yet
Come and write your comments
Links: