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Hello everyone, today we are going to learn about the LPC bus of Apple EC

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This lesson is divided into two parts

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introduction to Apple EC's LPC bus and Apple EC's LPC bus conditions

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First, let's take a look at the introduction to the Apple EC's LPC bus

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The EC in the Apple mainboard connects to the chipset through the LPC bus,

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which is like this architecture

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The EC is connected to the PCH through the LPC bus

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and also to a diagnostic interface, DEBUG,

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for connecting diagnostic cards or diagnostic devices

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The LPC bus conditions of Apple EC are divided into:

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LPC bus power supply, LPC bus clock, reset, address data composite line and frame period

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The LPC bus supply is commonly known as VDD in circuit diagrams, and the voltage is 3.3V

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The LPC bus clock is commonly named LPC_CLK24M_SMC in circuit diagrams,

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which represents the 24M LPC bus clock frequency

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This pin is the 24M LPC bus clock pin

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The common name for LPC bus reset is SMC_RESET_L

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and the voltage is 3.3V,

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which is the pin in the circuit diagram

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Next is the address data composite line of the LPC bus

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This is used to transmit address data between the EC and the PCH

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It is bidirectional communication, there are four lines in total

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LPC_AD0, LPC_AD 1, LPC_AD2, and LPC_AD3.

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From 0 to 3, there are four lines in total

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Finally, the frame period, commonly known as LPC_FRAME_L

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This is the pin in the circuit diagram

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This signal is also active at low level

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When it is low, indicates to start or end an LPC data transfer

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The preceding LPC bus power supply, LPC bus clock,

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and LPC bus reset are necessary conditions for the LPC bus to work

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During data transmission, we can measure the waveform

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on the address data composite line and frame period signal line of the LPC bus

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At the same time, we can connect the diagnosis card on the LPC bus

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to observe the self-check process of the mainboard in the soft start process

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Well, that's the EC's LPC bus