1
00:00:00,300 --> 00:00:04,433
Hello everyone, today we are going to learn about the boot timing sequence
2
00:00:05,566 --> 00:00:07,933
This lesson includes two aspects,
3
00:00:08,766 --> 00:00:11,933
one is the explanation of the boot timing signal,
4
00:00:12,533 --> 00:00:15,366
the other is the introduction of boot process
5
00:00:16,133 --> 00:00:20,400
First, let's look at the boot timing signal explanation
6
00:00:22,800 --> 00:00:25,700
When the previous standby conditions are normal,
7
00:00:26,166 --> 00:00:30,166
after receiving this PWRBTN# trigger signal,
8
00:00:31,300 --> 00:00:43,166
the PCH of the 100 series chipset will pull up the following signals to high level, SLP_S5#, SLP_S4#, SLP_S3#, etc.
9
00:00:50,166 --> 00:00:54,066
SLP_S5# indicates to exit the shutdown state
10
00:00:55,866 --> 00:01:02,566
SLP_S4# is used to enable power supply for S3 state, such as memory power supply
11
00:01:05,933 --> 00:01:11,166
SLP_S3# will be used to enable the power supply required by the S0 state,
12
00:01:11,366 --> 00:01:15,633
such as bus power supply, CPU power supply, etc
13
00:01:16,233 --> 00:01:23,733
In the 100 series chipset, this SLP_A# is no longer used because the ME module is powered off
14
00:01:24,300 --> 00:01:29,500
Once this SLP_A# was used to turn on the power supply of the ME module
15
00:01:29,800 --> 00:01:32,500
Now there is no need for it to exist,
16
00:01:33,966 --> 00:01:39,366
since the ME module power supply has been removed from the 100 series chipset
17
00:01:40,866 --> 00:01:48,400
SLP_LAN# and SLP_WLAN# are used to enable the power supply of the network adapter
18
00:01:49,633 --> 00:01:54,533
This signal is used only when some Intel original NICs are used
19
00:01:56,466 --> 00:01:59,866
In most models, these two signals are not used
20
00:02:02,166 --> 00:02:07,633
SLP_S0#, this signal is not present in the standard timing diagram,
21
00:02:08,200 --> 00:02:10,833
but it is present in the actual circuit
22
00:02:11,433 --> 00:02:18,466
This signal is used to control the CPU power supply into light load mode when the PCH and CPU are idle
23
00:02:19,633 --> 00:02:25,066
This signal can also be connected to the EC for other power management purposes
24
00:02:29,066 --> 00:02:31,166
Now let's look at the boot process
25
00:02:32,766 --> 00:02:37,700
For a computer to be turned on, the EC and PCH must be involved
26
00:02:39,266 --> 00:02:47,133
In the first step, the EC must meet standby power supply, standby clock, and standby reset requirements
27
00:02:47,833 --> 00:02:54,100
The EC program is read, the pin is configured, and the adapter is detected
28
00:02:55,666 --> 00:03:01,266
The LID# signal is high level, and the switching signal is also high level
29
00:03:01,600 --> 00:03:03,900
If these conditions are satisfied,
30
00:03:04,666 --> 00:03:09,500
we press the switch, it will generate a high- low- high level jump
31
00:03:10,566 --> 00:03:15,400
That is, when we press the switch, the signal will be pulled down,
32
00:03:17,100 --> 00:03:21,100
and when we release the switch it will return to the high level
33
00:03:21,666 --> 00:03:23,833
After receiving the switching signal,
34
00:03:24,400 --> 00:03:29,266
the EC will delay sending out a high- low- high pulse to the PCH pin
35
00:03:29,966 --> 00:03:37,166
When all the 10 standby conditions of PCH are normal, these include the top 4 standby conditions of RTC,
36
00:03:38,166 --> 00:03:44,066
as well as the deep sleep standby condition and the light sleep standby condition
37
00:03:44,700 --> 00:03:50,900
The PCH sends out the SLP_S*# signal to turn on the power supply of the following power supply
38
00:03:51,666 --> 00:03:53,700
Ok, this is the boot process