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Hello everyone, today we are going to learn the distribution of each clock signal

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First of all, when the PCH power supply is normal,

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its 24MHz crystal oscillator will start to vibrate,

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providing a reference frequency to the clock module inside the PCH

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After the PCH reads the ME firmware,

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the internal clock module is initialized, and the PCH emits various clocks

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This includes the 100M clock frequency assigned to the CPU,

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24M clock frequency, and each PCIE bus clock and LPC bus clock

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During the maintenance, we usually measure the LPC bus clock and PCIE bus clock

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to determine whether the clock signal is normal

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Here, the 100M clock of the CPU, the 24M clock,

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and the LPC bus clock to the EC do not require a clock request signal,

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while the PCIE bus clock does require a request signal

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For example, a 100M PCIE bus clock signal is given to a graphics card

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The PCH will output the corresponding PCIE 100M clock

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only after receiving the REQ# request signal from the graphics card

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When the PCH receives the REQ# request signal from the network adapter,

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it issues the 100 MB PCIE bus clock required by the network adapter

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The request signals are low active

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Whoever pulls down, it is sent to it

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In addition, the 100M PCIE bus clock and the 100M clock and 24M clock required by the CPU

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These are all required by differential transmission,

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they are one-to-one pairs

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Ok, so that's the distribution of the clock signals