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Hello everyone, in this lesson,

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we will learn the timing sequence generation of reset signal and integrated graphics card power supply

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This lesson consists of two parts

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First, the reset signal and the integrated graphics card power supply timing sequence generation

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Second, the distribution of reset signals

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First, let's look at the timing of the reset signal and the integrated graphics card power supply

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Let's look at the explanation of these signals

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The first one is called Platform reset,

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abbreviated PLTR #, 3.3V

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This signal is usually given to each chip and slot as a reset

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For example, the LPC bus to network card, WIFI, independent graphics card and EC

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When the platform reset is normally,

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the CPU also receives the power good signal PROCPWRGD

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and it will send the SVID signal to the CPU power supply chip

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to control and adjust the CPU core power supply

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This VCCCORE_CPU is the adjusted core power supply

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Once the CPU is powered and reset,

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it starts to issue addressing instructions to find the BIOS address

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It will send this address finding instruction through the DMI bus to PCH,

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PCH through the SPI bus to read the BIOS program,

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and begin to self-check the entire mainboard circuit

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During the self-test, when the memory is detected,

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PCH will send a memory reset signal, DRAM_RESET#

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After self-checking the memory,

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the CPU will send out SVID signal to control the generation of integrated display power supply, VCCGT

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Next, let's look at the distribution of reset signals

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In fact, when the platform reset is issued, the CPU reset is also issued

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Platform reset is called PLTRST#, and it is given to network card, EC, graphics card,

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and various slots, mainly for external devices

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The CPU reset is called PLTRST_CPU#, or PLTRST_PROC#

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and is a separate reset signal sent to the CPU to initialize it

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Another is memory reset

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It is sent to the memory slot by the PCH when the self-check memory is found during the startup self-check

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In this distribution, we can see that the platform reset is given to the graphics card, network card,

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M.2 interface, EC, and DEBUG chips and slots

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The CPU reset signal is only given to the CPU,

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and the memory reset signal is only given to the memory

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Okay, this is the reset signal distribution