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Hello everyone, today we will learn about the hard boot process of Intel 100-300 series chipset mainboards

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After installing the 3V button battery,

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first it will generate VCCRTC power supply to provide power to the RTC circuit of the bridge

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The RTC circuit of the bridge includes the four conditions of VCCRTC, RTCRST#,

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SRTCRST# and 32.768KHz crystal oscillator

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When we plug in the battery or adapter,

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a common point will be generated through the protective isolation circuit

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Then the standby power supply of EC will be generated

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After the EC standby power supply is normal,

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the EC supplies power to the crystal oscillator pin to generate the EC standby clock

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But now many ECs have the built-in clock

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Then the EC's standby power supply is delayed by resistors and capacitors to generate an EC standby reset

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There are also some EC standby resets that are pulled up internally by the EC

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After the EC's power supply, clock, and reset are all satisfied,

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the EC will read the program and configure its own pins

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Some EC programs exist inside the EC, and some exist outside the EC.

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After reading the program, it mainly configures the GPIO pins of the EC

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Before the GPIO pins are not configured, many functions of the EC cannot work normally

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Next, let's take a look

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There are two ways to generate power for the bridge,

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one supports deep sleep, and the other does not support deep sleep

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Those who support deep sleep start from step 4 and step 5 in the block diagram

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Machines that do not support deep sleep start with steps 4, 5 outside the block diagram

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Let's take the example of not supporting deep sleep

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After the EC reads the program and configures the pins, if the EC detects the adapter

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EC will automatically turn on the bridge standby power supply VCCDSW_3P3 (deep sleep standby power supply),

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and its main standby power supply VCCPRIM_3P3 and VCC PRIM_1P0

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There is a VCCPRIM_1P8 here, which is the main standby power supply of 1.8V,

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only available in the 300 series chipset

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The 1.8V standby power supply is not available in the 100-200 series chipset

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Some machines need to press the switch to turn on the bridge standby power supply

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Then, the EC delays to send a good standby voltage signal

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to the DSW_PWROK and RSMRST# pins of the bridge to notify the bridge that the standby voltage is normal

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The bridge we are talking about here refers to the PCH

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Next, press the switch, after the EC receives the switch signal,

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the EC delays and sends a "high- low- high" jump pulse signal to the PWRBTN# pin of the bridge

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After the bridge receives this switch signal, it will send high-level SLP_S5#, SLP_S4#, SLP_S3#, etc.

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Among them, SLP_S5# or SLP_S4# will control the main power supply of the memory to 1.2V,

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the VPP power supply of the memory to 2.5V, etc.

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SLP_S3# will control the generation of secondary voltages of 3.3V and 5V,

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as well as secondary voltages of 1.0V and 1.2V

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Like this VCCPLL_OC power supply 1.2V,

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it is also converted from the main memory power supply of 1.2V

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Including VCCST, VCCPLL and other 1.0V power supplies,

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most of them are converted from the 1.0V standby power supply, which is also a secondary voltage.

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After each power supply is normal,

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a VCCST_PWRGD signal will be generated and sent to the CPU

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The CPU will send a DDR_VTT_CNTL signal to control and generate the 0.6V VTT power supply of the memory

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After each power supply is normal, an open signal to the CPU power supply is generated

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It controls the generation of CPU power supply VCCSA, and CPU core power supply VBOOT voltage

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This VBOOT voltage is also called the startup voltage

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The VBOOT voltage value can be set through the pins of the CPU power supply chip,

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some are set to 1V, and some are set to 0V

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After each power supply is normal,

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the 24MHz crystal oscillator of the bridge will start to vibrate

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Then PG summarizes, successively generates PCH_PWROK and SYS_PWROK to the bridge

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After the bridge receives PCH_PWROK, it will read the ME firmware in the BIOS

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After reading the ME, the bridge will send out clocks

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Then the bridge sends PROCPWRGD to the CPU to notify the CPU that the core power supply is normal

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Then the bridge delays and sends a platform reset PLTRST#,

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which is usually sent to the LPC bus, to Wifi, some slots and independent graphics card, etc.

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The bridge then delays to send the CPU reset signal to the RESET# pin of the CPU

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Common names of reset signals are PLTRST_PROC# or PLTRST_CPU#

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The CPU sends out SVID waveform to the CPU power supply chip,

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which is used to adjust or turn on the CPU core power supply

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If the CPU core power supply is already at a high level when VBOOT voltage is generated,

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then it will adjust the CPU core power supply through SVID at this time

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If the VBOOT voltage of the CPU is 0V,

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it will turn on the CPU core power supply through SVID at this time

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After the CPU power supply is normal and has received signals such as reset and clock

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The CPU will go to the bridge through the DMI bus,

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and then read the BIOS through the SPR bus of the bridge, and start self-testing the entire mainboard

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When the memory is checked,

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the bridge will read the SPD information of the memory through the system management bus

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Then the bridge sends out a memory reset signal, DRAM_RESET#

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After checking the memory, the CPU will send the SVID waveform again to the CPU power supply chip,

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which is used to control the generation of integrated display power supply VCCGT

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But for most models, the integrated display power supply will be turned off in an instant

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Other power supplies can be shared inside the CPU

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When the program consumes a lot of graphics card,

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the integrated display power supply will be awakened again

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Ok, this is the hard boot process of Intel 100~300 series chipset mainboards