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147. Apple A2159 timing analysis- Power-on circuit
We will learn about the power-on circuit in the Apple A2159 circuit.
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Hello everyone, today we will learn about the power-on circuit in the Apple A2159 circuit

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Apple A2159 uses Intel's eighth-generation processor

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Therefore, when we analyze the boot circuit,

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we need to analyze it according to the timing of Intel's eighth-generation CPU chipset

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We have introduced the standby conditions of the T2 chip and CPU in the previous course,

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today we will look at the power-on circuit

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First, the switch key is connected to the connector J6600 of the mainboard

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When we press the switch, a "high --> low --> high" pulse signal is generated to the power chip

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The name of this switch signal is called PMU_ONOFF_L

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After the power supply chip receives the switch signal,

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it sends a "high --> low --> high" pulse jump from the SYS_BTN pin to the PWRBTN# pin of the CPU

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The name of this switch signal is PCH_PWRBTN_L

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After the CPU meets the standby condition and receives the switch signal,

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it will send out various signals such as SLP_S5#, SLP_S4#, SLP_S3#, etc.

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But in this machine, the SLP_S*# signal is not used

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After the CPU receives the switch signal,

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it will communicate with the T2 chip through the eSPI bus

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At the same time, the CPU will send a CPU_C10_GATE* open signal to the power chip

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After the T2 chip receives the power-on command transmitted by the eSPI bus,

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it will communicate with the power chip through the I2C bus

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The power chip will send out various EN signals to turn on the subsequent power supplies

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Ok, this is the power-on circuit for the A2159

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