1

00:00:00,600 --> 00:00:06,833

Hello everyone, today we will learn about the distribution of clock signals in the Apple A2159 circuit

2

00:00:08,100 --> 00:00:13,333

When we talked about power supply, PG, clock, and reset circuit in the last video,

3

00:00:13,733 --> 00:00:18,066

we introduced its step 44, the CPU outputs various clocks,

4

00:00:19,833 --> 00:00:21,800

so what are the various clocks here?

5

00:00:22,166 --> 00:00:23,133

Let's take a look

6

00:00:25,566 --> 00:00:28,333

This whole block diagram is about the clock signal

7

00:00:32,500 --> 00:00:34,233

After each power supply is normal,

8

00:00:35,266 --> 00:00:39,200

the 24MHz crystal oscillator of the CPU starts to vibrate,

9

00:00:39,466 --> 00:00:44,300

and the external name is PCH_CLK24M_XTALIN

10

00:00:47,800 --> 00:00:50,400

This pin is connected to the pin of the crystal

11

00:00:56,566 --> 00:01:01,033

The location number of the crystal oscillator is Y1900

12

00:01:03,200 --> 00:01:08,966

After the crystal oscillator starts to vibrate, it provides the CPU with a reference clock frequency

13

00:01:12,033 --> 00:01:15,000

Then, this clock module will output various clocks

14

00:01:15,866 --> 00:01:16,966

Let's find out

15

00:01:20,800 --> 00:01:29,900

First, CLKOUT_PCIE_N0 and CLKOUT_PCIE_P0, this is a pair of PCIE bus clocks

16

00:01:30,833 --> 00:01:35,633

It has group 0, group 1, group 2, until group 5,

17

00:01:35,833 --> 00:01:38,800

a total of 6 groups of PCIE bus clocks

18

00:01:45,966 --> 00:01:50,466

Each group has a clock request signal, which is active at low level

19

00:01:56,066 --> 00:02:00,666

When the request signal is low, the CPU will output a corresponding set of clocks

20

00:02:02,300 --> 00:02:06,600

If the request signal is always high, the CPU will not output the clock

21

00:02:11,033 --> 00:02:14,566

External names starting with NC are floating and not used

22

00:02:17,766 --> 00:02:21,000

This is the clock used for DEBUG diagnosis

23

00:02:23,266 --> 00:02:27,700

The following group is sent to the SOC, that is, to the T2 chip,

24

00:02:33,233 --> 00:02:36,266

and the T2 chip pulls down the clock request signal

25

00:02:38,400 --> 00:02:43,166

CPU will output this set of 100MHz PCIE bus clock to the T2 chip

26

00:02:46,733 --> 00:02:49,266

PCIE bus clocks are differential clocks

27

00:02:50,066 --> 00:02:53,000

The following group is for the TBT Thunderbolt chip

28

00:02:56,733 --> 00:02:59,833

Next, the group starting with NC is not used

29

00:03:02,333 --> 00:03:07,000

The fourth group below, this is the PCIE bus clock for the wireless network card

30

00:03:09,366 --> 00:03:12,433

After the wireless network card lowers the request signal,

31

00:03:14,533 --> 00:03:19,633

the CPU will output a corresponding set of PCIE bus clocks to the wireless network card

32

00:03:23,800 --> 00:03:26,533

The following one is also floating and not used

33

00:03:28,933 --> 00:03:32,600

Then, here is a set of test clocks, which are also not used

34

00:03:36,666 --> 00:03:38,966

OK, next, here are a few signals

35

00:03:44,500 --> 00:03:48,600

First of all, this is the reset signal of the RTC circuit,

36

00:03:51,033 --> 00:03:54,833

it does not belong to the clock circuit, it belongs to the RTC circuit

37

00:03:55,866 --> 00:04:05,066

RTCX1/ RTCX2, these two pins were originally connected to the 32.768KHz crystal oscillator of the RTC circuit

38

00:04:05,800 --> 00:04:08,633

But here they are not connected to the crystal oscillator,

39

00:04:08,933 --> 00:04:14,233

but the 32.768KHz clock is provided externally to the RTC circuit

40

00:04:17,466 --> 00:04:19,833

This is from the PMU power chip

41

00:04:20,933 --> 00:04:27,233

This pin is grounded through a resistor, and this CLKIN_XTAL is the input clock

42

00:04:27,733 --> 00:04:31,233

This is also grounded through a resistor and is not used

43

00:04:31,633 --> 00:04:36,033

These two pins are grounded through a resistor, which are also not used

44

00:04:37,866 --> 00:04:43,233

This is the pin connected to the 24MHz crystal oscillator, which we just introduced

45

00:04:43,633 --> 00:04:49,300

SUSCLK is the 32.768KHz clock output by the PCH,

46

00:04:49,933 --> 00:04:52,933

which is generally not used by external circuits, it is floating

47

00:04:54,300 --> 00:04:56,866

Ok, this is the distribution of the clock signal