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Hello everyone, today we will learn the standard timing of AMD Ryzen APU chipset

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In the AMD Ryzen APU standard timing,

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VDDBT_RTC_G is the power supply for the RTC circuit, 3.3V.3V

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X32K_X1 and X32K_X2, these two pins are the pins connected to the 32.768KHz crystal oscillator

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When the APU is powered by the RTC, it will provide power to the crystal oscillator pin,

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and the crystal oscillator will start to vibrate,

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providing the APU with a reference clock frequency of 32.768KHz

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RTC circuit does not participate in triggering

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When this power supply is pulled low, it will clear the CMOS settings

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However, if the RTC circuit is abnormal, it will cause other strange faults,

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such as no reset after booting, no running code (no self-test), etc.

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S5 POWER RAILS, this is the standby power supply in S5 state,

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including VDD_33_S5, VDD_18_S5, VDDP_S5

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They are 3.3V standby power supply, 1.8V standby power supply and 0.75V standby power supply

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After these three standby power supplies are normal,

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a standby power good signal RSMRST_L, 1.8V will be generated

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There is no deep sleep standby in AMD's timings

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PWR_BTN_L, this is the switch trigger signal for the APU

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When the signal is in standby, it is high level, it will be pulled low after pressing the switch,

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and it will return to high level after releasing the switch

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When the APU receives the switch trigger signal,

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it will set SLP_S5_L and SLP_S3_L high in turn to turn on the memory power supply

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and the power supply required by the S0 state

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In AMD's chipset, there are only SLP_S5_L and SLP_S3_L, and they came out at the same time

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When all the power supplies in the S0 and S3 states are normal,

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a power good signal PWR_GOOD will be generated and sent to the APU,

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indicating that the power supply on the mainboard is all normal

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At the same time, after each power supply is normal, the 48MHz crystal oscillator of the APU will start to vibrate,

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providing the reference clock frequency of the clock module inside the APU,

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and the APU outputs various clocks, including PCIE bus clock 100MHz,

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LPC bus clock 24MHz or 33MHz

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Then the APU sends a PWROK signal to the CPU power supply chip

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Then APU will send SVID signal to the CPU power supply chip to adjust the CPU core power supply

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The APU delays and sends out the PCIE reset signal PICE_RST_L,

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which is usually used to reset the independent graphics card

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APU sends out APU_RST# or RESET_L, which are platform resets,

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used to reset various devices on the platform, such as wireless network card, network card, EC, etc.

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Ok, here is the standard timing for the AMD Ryzen APU chipset