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174.Intel 10th~12th Deep sleep standby conditions
We will learn about the deep sleep standby conditions in the standard timing of Intel's 10th to 12th generation low-power CPU chipsets
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Hello everyone, today we will learn about the deep sleep standby conditions

in the standard timing of Intel's 10th to 12th generation low-power CPU chipsets

Deep sleep standby conditions include VCCDSW_3P3, DSW_PWROK, and BATLOW# these three signals

The first one, VCCDSW_3P3, is the CPU's deep sleep standby power supply, 3.3V

When deep sleep is not supported,

this power supply is generated simultaneously

with the main standby power supply VCCPRIM_3P3

When deep sleep is supported, the deep sleep standby power supply is generated before VCCPRIM_3P3

The second one, DSW_PWROK, this is the CPU's deep sleep standby power good signal, 3.3V

When deep sleep is not supported, this signal is connected with the main standby power good signal RSMRST#

The third one, BATLOW#, it is the low battery indication signal received by the CPU

When it is low, it means that the battery power is low

In the circuit, the signal is pulled up by the deep sleep standby power supply, controlled by EC or other circuits

OK, this are the deep sleep standby conditions

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