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In this lesson, we will learn about the power supply generation sequence

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in the standard timing of Intel's 10th to 12th generation low-power CPU chipsets

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This lesson includes two parts, the explanation of each power supply and signal,

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and the timing of each power supply and signal generation

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First of all, let's take a look at the explanation of each power supply and signal

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power supply in this timing diagram refers to this part

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The first one is VCCST power supply and VCCSTG power supply, which is the maintain voltage of the CPU,

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usually controlled by CPU_C10_GATE#

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The second one, VPP, VDD2 and VDDQ, these refer to the power supply required by the memory,

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generally controlled by SLP_S4#

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VCC refers to the secondary voltage 3.3V, the secondary voltage 5V,

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and the secondary voltage 1.8V, etc.

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After the VCCST power supply is normal,

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it will generate a VCCST_PWRGD signal to the CPU, 1.05V,

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indicating that the VCCST power supply is normal

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The CPU will then issue DDR_VTT_CTL to generate the memory VTT power supply, 0.6V

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Then, after circuit conversion, a VR_ON signal is generated,

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which is a signal to turn on the CPU power supply,

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and is used to turn on VCCIN to supply power to the CPU

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VCCIN is equivalent to supplying power to the common point inside the CPU

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The CPU integrates integrated display power supply, VCCSA power supply, VCCPLL power supply, etc.

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VCCIN is what we call the common point power supply inside the CPU,

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using FIVR power supply mode

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Next, let's take a look at the timing of each power supply and signal generation

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After the CPU receives the switch signal,

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it will directly or indirectly turn on the various power supplies behind

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through the ESPI bus or SLP_S4#, SLP_S5#, SLP_S3#, etc.

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Among them, SLP_S4# will be used to turn on the memory VPP power supply 2.5V

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and memory main power supply 1.2V

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SLP_S3# will be used to turn on the secondary voltage 3.3V, secondary voltage 5V, 1.8V, etc.

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After each power supply is normal, VCCST_PWRGD will be generated and sent to the CPU

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The CPU will issue DDR_VTT_CTL to control the VTT power supply of the memory, 0.6V

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At the same time, the CPU will issue a CPU_C10_GATE# to turn on the VCCSTG power supply of the CPU

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Ok, this is the generation sequence of each power supply and signal