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Hello everyone, today we will learn about the generation sequence of PG and clock signals

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in the standard timing of Intel's 10th to 12th generation low-power CPU chipsets

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PG, clock signal generation sequence refers to this part of the timing diagram

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The first one is VCCIN_VR_READY, which means that the VCCIN power supply of the CPU is normal,

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and it is usually sent to EC or communicated with other PGs.

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The second one, PCH_PWROK,

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this is the 3.3V high level sent to the CPU by the motherboard after the power supply is normal,

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indicating that the S0 state voltage is OK

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VCCIO, the actual circuit diagram searches for VCCIO_OUT,

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which is the 1.05V power supply output by the CPU

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After each power supply is normal, the 38.4M crystal oscillator of the CPU starts to vibrate,

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providing the reference frequency for the clock module inside the CPU

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But this crystal oscillator is not reflected in the standard timing diagram

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Next, PCH_CLK_OUTPUTS, this is the clock output by the CPU

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These include ESPI bus clock, PCIE bus clock, independent graphics card clock, etc.

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The last one, SYS_PWROK,

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means that the system power supply is normal,

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and it is also the key PG signal for reset, with a voltage of 3.3V

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Ok, this is the generation sequence of PG and clock signals