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Hello everyone, today we will learn about the distribution of clock signals

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in the standard timing of Intel's 10th to 12th generation low-power CPU chipsets

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First of all, after each power supply is normal, the 38.4M crystal oscillator of the CPU starts to vibrate,

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and provides the reference clock frequency for the clock module inside the CPU

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After the CPU internal clock module is initialized,

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the internal clock module will reduce and multiply the frequency of the 38.4M crystal oscillator

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to generate various clock signal outputs,

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which are respectively sent to the various peripherals, such as memory, independent graphics card,

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network card, M.2 interface, solid state drive and EC

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Among them, the two sets of clocks for the memory do not require request signals

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All PCIE bus clocks can be sent only after receiving the corresponding request signal

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For example, the 100M PCIE bus clock for the independent graphics card,

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it can be sent out after the CPU receives the low-level REQ# request signal from the independent graphics card

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The ESPI bus clock is usually 60M, but this clock can be defined by the program

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So this eSPI bus clock is custom

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Ok, here is the distribution of each clock signal