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Hello everyone, today we will learn about the reset signal generation sequence

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in the standard timing of Intel's 10th to 12th generation low-power CPU chipsets

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This lesson includes reset signal generation sequence, and reset signal distribution block diagram

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The generation timing of the reset signal refers to this part of the timing diagram

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The first one is PLTRST#, which is the platform reset signal, 3.3V,

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sent by the CPU to each chip and each slot as a reset

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This is the over temperature protection signal

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After reset, the CPU will send an SVID signal to the CPU power supply chip to adjust the CPU power supply VCCIN

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SVID usually consists of a serial bus consisting of a data (VIDOUT) and a clock (VIDSCK),

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and an ALERT# signal

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The third is the memory reset, DRAM_RESET#

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After the various power supplies, clock, and reset signals of the CPU are normal,

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it will start to read the BIOS and start self-test

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In the self-test process,

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when the CPU completes the identification of the memory through the system management bus,

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it will send DRAM_RESET# to the memory to reset the memory and initialize the memory

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Ok, this is the sequence timing of the two reset signals

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Next, let's take a look at the distribution block diagram of the reset signal

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Platform reset is mainly for graphics cards, network cards, and M.2 interfaces,

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And for the LPC bus of EC, the DEBUG diagnostic interface

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There is also an independent memory reset signal here,

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which is usually pulled up by the main power supply of the memory to provide reset for the memory

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Ok, here is the distribution block diagram of the reset signals