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Hello everyone, today we will learn about the generation timing of the PG signal, clock signal,

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and reset signal of the Wistron 15221 motherboard.

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We have learned the various power supplies enabled by SLP_S3# and SLP_S4# in the previous course

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Among them, after the 1D5V_S0 power supply is normal, the 1D5V_S0_PWRGD signal will be generated

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It was renamed ALL_SYS_PWRGD and VR_EN

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ALL_SYS_PWRGD leads to the VCCST_PWRGD pin of the CPU and the EC

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VR EN is sent to the open pin of the CPU power supply chip

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When the CPU power supply chip gets the open signal, it will control the generation of VCCSA power supply

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The power good signal (IMVP_PWRGD) is renamed PCH_PWROK through a resistor,

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and sent to the PCH_PWROK pin of the bridge

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When these various power supplies are normal,

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the 24MHz crystal oscillator of the bridge starts to vibrate

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After the bridge receives PCH_PWROK, it will read the BIOS through the SPI bus

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Mainly read bridge pin configuration program and ME (Intel庐 Management Engine) firmware

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Then the bridge internally completes the initialization of the clock module, and sends out various clocks

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After the EC receives ALL_SYS_PWRGD,

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it sends SYS_PWRGD to the SYS_PWRGD pin of the bridge with a delay of 100 milliseconds

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The bridge sends PROCPWRGD to the CPU to notify the CPU core that the power supply is normal

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Then, the bridge delays to send a platform reset signal,

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which is sent to the solid state drive, GPU, network card and EC respectively.

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Then the bridge sends the reset signal of the CPU (PLTRST_CPU#) to the RESET# pin of the CPU.

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When the CPU's power supply, clock, reset... are all normal,

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the CPU will send out SVID waveforms to the CPU power supply chip to control the core power supply of the CPU

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After the CPU core power supply is normal, start to send "addressing instructions" through the

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DMI bus, and read the BIOS through the bridge

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After the bridge receives the "addressing instruction" sent by the CPU,

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the bridge reads the BIOS again through the SPI bus.

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After reading the BIOS, the bridge returns the BIOS program to the CPU through the DMI bus

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The CPU will call the self-test program in the BIOS to perform a self-test on the entire platform

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The first is to initialize the chipset

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After the chipset is initialized successfully, the bridge will read the memory (SPD) chip information through SMBUS

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There is a prerequisite here,

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that is, the chip power supply of this memory (SPD) must be normal

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This power supply is usually provided by 3D3V_S0

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When we measure the SMBUS waveform, we can measure it at pins 253 and 254 of the memory slot

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After the bridge reads the memory,

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it will issue a memory reset signal (DRAM_RESET#) to initialize the memory particles

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After self-testing the memory, the CPU will store the BIOS self-test program into the memory

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And call the self-inspection program from the memory to self-inspect each device

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Then the CPU will send out the SVID waveform to turn on the integrated display power supply

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Well, this is the generation timing of PG signal, clock signal and reset signal