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220. Loongson LS7A1000 chipset standard timing- Power supply condition
220. Loongson LS7A1000 chipset standard timing- Power supply condition after startup
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Hello everyone, today we will learn about the power supply conditions after power-on

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in the standard timing sequence of Loongson's LS7A1000 chipset

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The power supply condition after standby refers to: after the above standby conditions are normal,

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the chipset receives the "high-low-high" ACPI_PWRBTNn switch signal,

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and the chipset will send out ACPI_S5n, ACPI_S4n, ACPI_S3n.....

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These signals are used to turn on the subsequent power supplies

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ACPI_S5n here is similar to SLP_S5 in Intel chipsets#

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ACPI_S4n and ACPI_S3n are equivalent to SLP_S4#, SLP_S3#... and other signals in the Intel chipset

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When these signals change from low level to high level, the subsequent IO_VDDE and Core_VDD will be turned on

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Usually, after ACPI_S5n changes from low battery to high level, the whole machine will exit the S5 state

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When ACPI_S4n is high level, control the whole machine to exit S4 state

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It is usually used to turn on the power supply required by the S3 state, such as memory power supply, etc.

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When ACPI_S3n is at a high level, it means exiting the S3 state,

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which is usually used to turn on the power supply required for the S0 state

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ACPI_SLPLANn is the opening signal of the network card power supply

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IO_VDDE represents a lot of power supply,

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including IO_3V3, DDR_VDDE/DDR_VREF and HT_1V8, HT_1V2...etc.

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These power supplies are explained in detail

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For example, IO_3V3 is the pin power supply of the low-speed IO port,

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and DDR_VDDE/ DDR_VREF is the power supply of the memory

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HT_1V8 is a super transmission port 1.8V power supply

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The so-called super transmission port here refers to the communication port

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between the chipset and the Godson CPU.

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HT_1V8 is also the 1.2V power supply for the Super Transmission port

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PEST_3V3 is the power supply for chipset PCIE module and SATA module

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GMAC_VDDE refers to the GMAC IO pin power supply,

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the voltage value needs to be consistent with the external PHY chip, usually 3.3V or 2.5V

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USB_A3V3 is the USB analog power supply

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Next, the Core_VDD, which includes the VDD core power supply

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PEST_1V 1 is also the power supply for the physical layer of the PCIE module and the SATA module 1.1V

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There is also PLL_HT_VDD, which is the analog and digital power supply for the PLL

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PLL_VDDA_CORE is the core phase-locked loop analog power supply

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There are also many power supplies for various graphic phase-locked loops in the back

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Ok, these are the power supply conditions after power on

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