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Hello everyone, today we will learn about the PG, clock,

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and reset signals in the standard timing sequence of the Loongson LS7A1000 chipset

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PG, clock, and reset signals refer to this part of the standard timing diagram

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After the above power supplies are normal, an ACPI_PWROK power good signal will be generated

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This signal means that the last stage power supply is powered on successfully, 3.3V

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Then, there is an ACPI_SYSRSTn, which is the system reset signal, active low,

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connected to the restart button, the voltage value is 3.3V

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The following is ACPI_SUSTATn,

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which controls the platform to enter a low power consumption state when the signal is low

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When working normally, it is 3.3V high level

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This ACPI_PLTRSTn is the platform reset signal, which works normally at 3.3V

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Next is the clock part

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The first clock CLKOUT100M, which is a 100MHz clock output

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It can also be used as the HT reference clock of the Godson-3 processor

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The second CLKOUT33M, this is the 33MHz clock output

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It can be used as a reference clock for the memory for the Godson-3 processor

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There are multiple sets of clock outputs like this 33MHz and 25MHz

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Next CLKOUT25M, which is a 25MHz clock output

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It can be used as the core reference clock for Loongson-3 processor, or as a GPIO pin

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The fourth CLKOUTFLEX, this is a variable frequency clock output,

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the default is 100MHz, it can be used as a GPIO pin

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The frequency of this pin can be defined according to the program,

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or set by some special pins of the chipset

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The above are the PG, clock, and reset signals after power-on