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Hello everyone, in this lesson we will talk about the power-on part of the hard boot of the 100 series mainboard

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In the previous lesson, the mainboard has generated SLP_S4# SLP_S3#

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And the power supply has started to work, outputting red 5V, orange 3V and yellow 12V

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Next, SLP_S4 will control the generation of 2.5V VPP power supply, and 1.05V VCCST or VCCPLL power supply

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It then converts the control to generate the memory main power supply 1.2V

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It should be noted here that the power supply generation sequence described in the hard boot

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may be slightly different from the actual mainboard.

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But overall it's going in the right direction

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We look for SLP_S4 in the drawing to see what it controls

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Search for SLP_S4

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As you can see, its external name is N_S4_S5

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Search for this signal name

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It can be seen that it is sent to IO after it is issued by PCH

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After giving the IO, it also came to such a circuit

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Let's take a look at this circuit

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When SLP_S4 is high level, the B pole of DFQ3 is high level

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DFQ3 is an NPN transistor, high level conduction and low level cutoff

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When its B pole is in high level, it will be turned on, then the three pins will be pulled down to low level

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At the same time, the second pin of DFQ2, which is the B pole,

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will also be pulled down to low level.

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DFQ2 is an NPN transistor, it will be cut off when B is extremely low

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After the cut-off, its G pole will be pulled up to 5V

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This component is a MOS tube

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Here is the D pole, here is the S pole

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Here is also the D pole

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It is an N-channel MOS transistor

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Its G pole is 5V, and the D pole is connected to the 1V power supply generated during standby.

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When the G pole is 5V, it will be turned on, and the DS pole will be turned on,

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and the VCCST_VCCPLL power supply will be generated.

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This is the first power supply generated during power-up

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Let's draw this step

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So far, the first power supply VCST_VCCPLL after the trigger has been generated

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Let's see where else SLP_S4 went in the drawings

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You can see that it came to a circuit like this

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We can push this circuit from the back to the front

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If a high level VPP start signal is required, then MAQ7 will be cut off

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Its G pole will be low

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If its G pole is low, it must be grounded

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Then both MAQ8 and MAQ9 need to be turned on.

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The G pole of MAQ8 is connected to SLP_S4, which is high level

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At this time, only the signal MA_EN connected to the G pole of MAQ9 is also high.

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Let's see where MA_EN comes from

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As you can see, it comes from IO

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Let's see if it goes anywhere else

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Here it is pulled up by 5VDUAL

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There are no components installed here, all of them are crossed out

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There are no components installed here

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This MA_EN is only connected to this circuit and IO

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As long as IO receives SLP_S3 and SLP_S4, it will send MA_EN signal

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Let's draw this MA_EN signal first

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After having MA_EN, this circuit can work

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VPP25_EN came to this circuit, this is a small PWM circuit

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As long as there is power supply and open signal, it will have output

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The power supply comes from 5VDUAL, and the turn-on signal has just been generated

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With power supply and open signal, it will output VPP power supply

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Let's draw this step as well

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VPP power supply will also output a PG signal

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Well, the second power supply VPP power supply after the trigger has already been generated

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The VCCST/VCCPLL power supply has been generated,

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and at this time there is still a memory main power supply

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Let's find the main power supply of the memory in the physical picture

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Here is the memory slot

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The main memory power supply is usually located very close to the memory slot.

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There are two inductors here, both of them may be the main power supply of the memory

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However, under normal circumstances, the lower one is the 2.5V power supply,

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and the upper one is the main memory power supply.

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Let's confirm in the bitmap

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The output of the inductor above is VDDQ, which is the main power supply of the memory.

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The output of the inductor below is VPP25, which is the VPP power supply output by this circuit.

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How is the above power supply generated?

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Find this circuit in the circuit diagram

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It can be seen that it is also controlled by a PWM circuit

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This PWM circuit is relatively simple, it can work only with power supply and open signal

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Power supply comes from 5VDIAL, which has generated a

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The open signal is pulled up by 5VDUAL

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VPP25_PG has been generated here

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So the working condition of this circuit has been satisfied

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At this time, the memory power supply should have been generated

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Let's draw this step as well

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At this point, the memory main power supply has been generated

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Then to generate 1.05V VCCIO power supply

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We search for VCCIO in the circuit diagram to find the generation circuit of VCCIO

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VCCIO is converted from the main power supply of the memory by such an op amp plus MOS circuit

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For this circuit to work, VCCIO_EN_1 cannot be pulled low

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Let's take a look at where VCCIO_EN_1 is connected to

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It is renamed VCCIO_EN through a direct copper

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This signal is only controlled by IO

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When the IO receives the SLP_S3 signal, it will not pull down VCCIO_EN

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VCCIO_EN will be divided in series by VPP 2.5V, and a voltage of about 0.95V will be divided.

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Then it will control the operation of the op amp plus MOS circuit,

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and output a 0.95V VCCIO power supply

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The VCCIO here is 0.95V

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On some mainboards it is 1.05V

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OK, let's draw this step as well

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After having VCCIO, the next step is to generate the VCCSA voltage,

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and to generate the start signal of the CPU power supply

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Let's first look at the VCCSA voltage

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The VCCSA voltage is next to the VCCIO voltage,

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and it is also a power supply circuit for an op amp plus MOS.

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Its working conditions are the same,

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as long as VCCSA_EN is not pulled low, this circuit can work, and it will output VCCSA

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How can VCCSA_EN not be pulled down?

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Let's see where it connects

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It only connects the circuit below

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When both VDDQ and VCCIO are high, both DCQ3 and DCQ4 are turned on

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After conduction, the G pole of DCQ2 will become low level, and DCQ2 will be cut off

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Then VCCSA_EN will not be pulled down

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It won鈥檛 be pulled down, the above circuit will work, it will output VCCSA

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Both VDDQ and VCCIO have been generated, so VCCSA will also be generated now

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Let's draw this step as well

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So far, the VCCSA voltage has been generated, and the power-on part will come to an end for the time being.

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In the power-on part, a 2.5-volt VPP power supply is generated, VDDQ is generated, VCCIO,

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VCCSA, and VCCST_VCCPLL are generated

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Next, let's look at the PG and reset parts