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Hello everyone, in this lesson we will look at the PG and reset signals of the 100 series mainboards

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In the first step of the PG part, the power supply chip of the CPU sends a signal to the SYS_PWROK of the bridge

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This SYS_PWROK is a very critical PG signal, which controls the generation of platform reset

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First of all, we need to know what the signal from the CPU power supply chip is.

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This signal is VR_READY, which means that the CPU power supply chip is ready

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Let's find out where the CPU power supply chip is in the physical object

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It's here, its position number is DAU1

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Search for DAU1 in the circuit diagram

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Its VR_READY is on pin 11

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Then under what circumstances will the CPU power supply chip send out the VR_READY signal?

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The working conditions of the chip are basically satisfied,

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that is, the power supply and the opening signal are all normal,

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and it will send out the VR_READY signal

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Let's look at VDD first

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The external resistor of VDD is not installed

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Search to see where it goes

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It is connected to 5VDUAL through an N-channel MOS tube

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The G pole of this MOS tube is 12V

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That is to say, when the yellow 12V is normal,

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the 5VDUAL will be converted into the VDD and VDDP power supply here.

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VDDP is connected to VIN through a 2.2 ohm resistor here

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The VIN here is the 12V of the CPU power supply interface, which is the 12V of this position

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Below, VIN is connected to VIN, 12V

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The power supply is now all normal.

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Look at the opening signal

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The open signal here is pulled up by VIN through series voltage division

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It is connected to the IO

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When the IO receives the SLP signal, it will not pull down VTT_PWRGD

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If VTT_PWRGD is not pulled down, it will be pulled up to a high level of about 3V by VIN series voltage divider.

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At this time, there is an opening signal

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With power supply and open signal, then the chip is ready and will send out VR_READY signal

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Who is this VR_READY for?

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Let's search

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This VR_READY is given to IO

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Let's draw this part first

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After the power supply and start signal of DAU1 are normal, it will send a VR_READY signal to the IO

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After the IO receives this high-level VR_READY, it will immediately send out a VRMPWRGD

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Let's see where this VRMPWRGD connects to

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VRMPWRGD here is renamed CPU_VCCST_PWROK after series voltage division,

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and it is given to the VCCST_PWRGD pin of the CPU.

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VCCST_PWRGD is a key signal of the CPU

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When the CPU receives this VCCST_PWRGD, it will send the above DDR_VTT_CTL signal

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This signal is used to turn on the VTT power supply

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Let's see where else VRMPWRGD has gone

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This signal is renamed SYS_PWROK through a copper skin and given to the bridge

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At this time, the bridge receives the SYS_PWROK signal

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Let's draw this step

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Then this signal is also given to the CPU

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After the CPU receives VCCST_PWRGD, it will send a VTT open signal

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Ok, let's take a look at where the VTT start signal sent by the CPU goes

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The turn-on signal is changed to DDR VTT_EN through a 0 ohm resistor, and comes to MAU1

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When MAU1 receives VDDQ 5VDUAL and DDRVTT_EN DDRVTT_BOOT, it will send out DDRVTT power supply

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Here is another power supply

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Let's draw this step as well

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Next let's look at the next step

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The ATX power supply will delay sending the PG of the gray line to the IO

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This step is that the ATX power supply will delay for a period of time

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after the normal output and send a high level PG to the IO

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It is a gray line

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Let's find this circuit

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The eighth pin is PWOK

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PWOK will be given directly to IO

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IO will also detect the voltage of each channel and the PG of ATX

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After IO detects that all of these are normal, it will send a PG signal to PCH_PWROK

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Let's take a look at how IO detects various voltages

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Let's take a look at how IO detects various voltages

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These VIN pins are generated after each power supply is divided in series

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The IO is to detect the voltage through these VIN pins

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Among them, VIN1 detects the voltage of VCC33V

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After 3V is divided in series, it should be a 2V voltage

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VIN2 detects a voltage of 12V and it should also be 2V

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VIN3 detects the voltage of VCC 5V, which is also a series voltage divider of 2V

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VCC4 detects VCCGT, which is the integrated display power supply

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At this time, there is no integrated display power supply,

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so it cannot detect the integrated display power supply

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VCC5 is VCCSA

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VCCSA already has at this time

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VCC6 detects VDDQ, which is the memory power supply

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At this time it also has

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It can be seen that not all of its VIN pins are powered

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When the IO detects that part of the voltage is normal through the VIN pin,

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and the gray PG is also sent to the IO, the IO will send a POWER OK signal

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It is called ITE_PWROK here

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It was renamed O_PWROK after a exclusion

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After this O_PWROK went out, it was renamed as PCH_PWROK,

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and it was given to the PCH_PWROK pin of the bridge.

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Let's draw this step as well

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After the IO gets PG and the detection voltage is normal, it will send PCH_PWROK

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Ok let's move on

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After the bridge receives PCH_PWROK, the bridge will start working

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First of all, the 24M of the bridge needs to start to vibrate, and the bridge also needs to read the BIOS

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At this time, the bridge reads the ME in the BIOS

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We first find the 24M clock and BIOS, we first find them in the physical

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Bridge's 24M clock is here

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This crystal oscillator is the 24M crystal oscillator of the bridge

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And the BIOS is here

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At present, the BIOS of the desktop computer is eight-pin.

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Let's first look at the 24M crystal oscillator

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When the bridge gets PCH_PWROK and the power supply of the bridge is normal,

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the crystal oscillator will start to vibrate to provide a basic frequency for the bridge

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At the same time, the bridge also needs to read the BIOS

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The location number of the BIOS is M_BIOS

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We searched for this location number and found the BIOS chip

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The workflow of this BIOS chip will be described in detail later.

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Here we only need to know that the bridge will read this BIOS.

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When the bridge reads the BIOS, it uses the SPI bus

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SPI bus we count it as step 21

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After the bridge reads the BIOS, it will send a clock signal and send PROCPWRGD to the CPU

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Let's first talk about this clock signal

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Most of the devices on the mainboard need a clock signal to work, such as network cards or PCIE devices, etc.

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The clock signal they need is the clock signal from the bridge here

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This clock signal is not only given to a certain device, but multiple devices

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Although this clock signal is given to many places, there is one place where we can easily measure the clock,

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that is the A13 and A14 pins of the PCIE slot

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After the bridge sends out various clocks, pins A13 and A14 of the PCIE slot can measure a voltage of a few tenths of V

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Next we look at PROCPWRGD

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This signal is a good power signal sent by the bridge to the CPU, and the external name is N_CPUPWROK

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Let's just draw it

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When all these are output, the bridge will output a very critical signal, called the platform reset signal, PLTRST

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The platform reset signal will be given to the IO

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After IO receives the platform reset signal, it will send a reset signal to the network card or other PCIE devices

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After the platform reset signal is sent out, it will be sent to IO

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Let's find this platform reset signal in the circuit diagram

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Search PLTRST

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As you can see, this is the internal pin of the bridge.

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Its external name is N_PFMRST

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Search for this N_PFMRST

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As you can see, it gave the IO

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This platform reset signal is only given to IO

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After the IO receives this signal, it will send a reset signal to reset the PCIE slot and network card

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At the same time, the bridge will send another CPU reset signal, called PLTRST_CPU#

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Let's search for this signal

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As you can see, the external name of this signal is N_CPURST

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This signal is used to reset the CPU

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Let's continue to search for this external signal to see if it is given to the CPU

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This signal is directly connected to the CPU and given to the RESET# pin of the CPU to reset the CPU.

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Let's draw this step as well

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After the CPU receives the CPU reset signal, it will send an SVID signal to the CPU to power the chip

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This SVID signal is mainly used to adjust the CPU power supply voltage

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When the CPU power supply chip receives the SVID signal, it will output the CPU power supply

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Let's draw this step

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The SVID signal has three wires

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When the CPU power supply chip receives the SVID, it will output the CPU core power supply

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After the power supply of the CPU is satisfied, it will start to work,

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and it will read the BIOS through the bridge, and start self-checking and running code

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After self-checking the memory,

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the CPU will send another SVID signal to control the generation of integrated display power supply VCCGT

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So far, the power-on, PG and reset workflow of the 100 series is over,

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and the entire hard start of the 100 series is also over.